Why this value

Pick a value in the waveform and RTL++ builds the chain of causes behind it, from the netlist your test ran and the run itself. Each step is one line of your code, the values that mattered, and the time.

Asking

• Hold ⌥ and click a value in the waveform.
• Right click a signal name in the waveform and choose Why at the cursor time.
• With the cursor placed, the command bar offers Why is it its value for every signal of the design.

The chain opens in the right panel. Why needs a run: run a test first, and if the design has errors, fix them so it elaborates.

How the walk goes

• A value computed by logic is explained at the same moment: the line that computes it and its inputs then.
• A register is explained at its last active clock edge: the line that loaded it, the decisions on the way (which if branch, which case item), and its inputs just before the edge. A register that only held its value is explained at the edge that last loaded it.
• The walk follows the input whose value changed, so it heads for what is different rather than what was always so.
• A register loaded the same way edge after edge, such as a counter counting, is folded into one step with its first and last value.
• It stops at a primary input, a register holding its reset or initial value, a constant, or after 12 steps, and says which.

Using the chain

• Click a step to move the waveform cursor and the editor to it, and highlight its signal in the schematic.
• Click one of a step's input values to ask why about it in turn.

What it should have been

Type the value the signal should have had under Expected, as a Verilog literal (8'h4b), hex (0x4b), a number (75) or a state name. The walk then follows the inputs that disagree with what the logic needed, and marks the first step where reality and expectation part: usually the line with the bug.

When a failed test's message says what it wanted, such as count is 0, expected 9 or got 5a, expected 4b, Expected is filled in for you and says which test it came from.