For open FPGAs, you may not need Vivado or Quartus.
Build iCE40 and ECP5 designs in a browser on any computer, with no vendor install, and flash the board over USB.
RTL++, Vivado and Quartus
Vivado (AMD) and Quartus (Altera) are the tools for their own FPGAs. For Lattice parts there is an open flow, and it runs in the browser.
| Aspect | RTL++ | Vivado or Quartus |
|---|---|---|
| Runs on | A browser on macOS, Windows, Linux or ChromeOS | Windows or Linux |
| Install | None | A vendor download of tens of gigabytes |
| FPGAs | Lattice iCE40 and ECP5, 11 devices | The vendor's own: AMD for Vivado, Altera for Quartus |
| Bitstreams for AMD or Altera parts | No | Yes |
| Simulation | Icarus Verilog, checked by a second simulator on the netlist | The vendor's simulator |
| Timing | nextpnr's estimate, labelled as one | Vendor sign-off timing analysis |
| Flashing | iCEBreaker and ULX3S over USB from the browser | The vendor's hardware manager or programmer |
When you still need the vendor tools
Building for an AMD or Altera FPGA, using vendor IP such as memory controllers and transceivers, or signing off timing for production.
When you do not
Learning digital design, working on an iCE40 and ECP5 board, or testing and debugging RTL before it goes anywhere.
| Logic cells | 36 | of 5,280 |
|---|---|---|
| Flip-flops | 24 | of 5,280 |
| Carry | 21 | of 5,280 |
| Global buffers | 2 | of 8 |
| Block RAM | 0 | of 30 |
| DSP | 0 | of 8 |
| I/O | 3 | of 39 |
| PLL | 0 | of 1 |
clk reaches 58.98 MHz against a 12 MHz target. Estimate, nextpnr model for iCE40 UP5K (sg48), not sign-off.
Questions
Can I run Vivado on a Mac?
Not natively: Vivado and Quartus run on Windows and Linux. If your board has a Lattice iCE40 and ECP5 FPGA, RTL++ builds and flashes it from a browser on a Mac.
Is RTL++ a replacement for Vivado or Quartus?
Only for open FPGA flows. Bitstreams for AMD and Altera FPGAs need the vendor's tools. For iCE40 and ECP5 boards such as iCEBreaker, ULX3S and OrangeCrab, RTL++ goes from Verilog to a flashed board without them.
Which open source tools does it use?
Yosys for synthesis, nextpnr for place and route, Project IceStorm and Project Trellis packers for bitstreams, Icarus Verilog for simulation and openFPGALoader for flashing, all compiled to WebAssembly.
Can I take my Verilog to Vivado later?
Yes. A project exports as a zip of plain source files that any tool reads. Pin constraints are specific to each board and do not carry over between vendors.