Documentation
How RTL++ works, checked against the code that runs it.
Start here
What RTL++ is, your first project, the workspace, and the keys that make it fast.
- IntroductionRTL++ is a workspace for Verilog and SystemVerilog in the browser: write a design, run its tests in two simulators, trace any value to its cause, build for an open FPGA and flash the board.
- Your first projectOpen RTL++, create a project, run its test, read the waveform, change the design, and build it. Your first Verilog project in about two minutes.
- The workspaceThe regions of the RTL++ workspace: the top bar, the rail, the lenses, the waveform dock and the right panel, and the command bar that reaches all of them.
- Keyboard shortcutsEvery keyboard shortcut in RTL++ on Mac, Windows and Linux: running and building, the editor, the layout and the waveform.
Projects and files
Starting a project, where it is saved, the rtlpp.toml manifest, files, and moving projects in and out.
- Projects and savingHow to start a project, how RTL++ saves it on this device and in your account, and how to rename, duplicate, export or move a project to Trash.
- The rtlpp.toml manifestThe rtlpp.toml file that names a project's top module, board, device, constraint file and build settings, and where to change each one.
- FilesAdding, renaming, duplicating and deleting files in an RTL++ project, which files are compiled, and how the top module and constraint file are chosen.
- Import and exportBring an existing Verilog or SystemVerilog project into RTL++ as a zip, and export any project as a plain zip that builds with the open tools outside RTL++.
Editor
Diagnostics as you type, quick fixes, navigation across files, find and replace, and values from the waveform beside your code.
- DiagnosticsHow RTL++ checks Verilog and SystemVerilog as you type: full slang diagnostics for the design and its testbenches, source checks with quick fixes, and the Problems list.
- Navigation, find and replaceGo to a definition, find references and rename across files, hover a name for its declaration and value, and find and replace in the RTL++ editor.
- Values in codeWith the waveform cursor at a time, RTL++ writes the value of each signal after the line of code that names it.
Simulation and tests
How a testbench passes or fails, running tests from the rail, and why a pass needs two simulators to agree.
- TestbenchesHow RTL++ finds testbenches, the rules that decide pass and fail, and the PASS and $fatal convention every template follows.
- Running testsRun every test or one, read each result in words in the Tests rail, and jump from a failure to its waveform, its source or the assistant.
- Two simulatorsWhy an RTL++ test passes only when Icarus Verilog and a netlist simulator agree on every sample, what a disagreement means, and how unknown values are found.
Waveforms
Reading bits, buses, unknown and floating values, and moving through a run with two cursors.
Why this value
Trace any value in a run back through the logic and the clock edges that produced it.
Schematic and state machines
Views drawn from the elaborated design, linked to the code and the waveform.
- SchematicThe RTL++ schematic of the elaborated top module, one level of hierarchy at a time, cross-probed with the code and the waveform.
- State machinesRTL++ finds the state machines in your design and draws each one, with the state at the waveform cursor, how often each state was visited, and the arcs no test took.
Build
Synthesis, place and route and a bitstream in the browser, with utilization, timing and reproducible seeds.
- BuildingBuild an RTL++ project for an iCE40 or ECP5 FPGA in the browser: the steps, utilization against the device, maximum clock frequency, the worst paths and the bitstream.
- DevicesThe iCE40 and ECP5 devices RTL++ builds for in the browser, with the capacity of each as nextpnr counts it.
- Seeds and target frequencyMake an RTL++ build reproducible with its placement seed, hold every clock to a target frequency, and sweep seeds to see the spread.
Boards and flashing
The launch boards, the board lens that runs your design on a drawing of the board, and programming real hardware.
- Launch boardsThe FPGA boards RTL++ supports: the device, clock, starting template, constraint file and flashing route of each.
- The board lensSee your design drive a drawing of the board: LEDs, displays, buttons and switches, running live or at the waveform cursor.
- FlashingProgram an FPGA board from RTL++ over WebUSB in Chrome or Edge, what each failure means, and how to use the bitstream with openFPGALoader instead.
The assistant
What the assistant can read, change and run, how it proves what it says, and the allowance it draws on.
- Working with the assistantAsk the RTL++ assistant about a design, a failing test or a waveform. It reads your files, edits them, runs the tests, builds and traces values through the same engines you use.
- Evidence and editsHow the RTL++ assistant backs every claim of a pass, a fix or timing with a run, why it never weakens a test, and how to review and undo its edits.
- Models and allowanceThe assistant models in RTL++, which plans include them, and the allowance that RTL++ and Spice++ share.
Sharing and moments
Share a project by email or link at a role, comment together, and point someone at the exact test, time and line you are looking at.
Account and billing
One account, one plan and one assistant allowance for RTL++ and Spice++.
Can’t find it here
Ask the assistant in the workspace, or write to contact@surfplatforms.com.