Diagnostics
How RTL++ checks Verilog and SystemVerilog as you type: full slang diagnostics for the design and its testbenches, source checks with quick fixes, and the Problems list.
A short pause after you stop typing, Yosys with the slang frontend checks the whole design and every testbench in a worker. Errors and warnings appear as a quiet underline; hover one for the message and a one-line explanation. The pause is 0.8 s by default. Change it, or turn live diagnostics off, under Engines in the Inspector.
Source checks and quick fixes
RTL++ also checks for the mistakes that simulate one way and synthesize another. Where a fix is safe, it is offered on the warning.
| Check | What it finds | Quick fix |
|---|---|---|
| Sensitivity list | always @(a or b) that misses a signal the block reads | Use always_comb, or always @* in Verilog |
| Blocking assignment | = in clocked logic | Use non-blocking <= |
| Latch | A combinational block that leaves a variable unassigned on some path | Assign a default, or add a default item |
| Width mismatch | An assignment whose sides have different widths, with both widths | None |
| Random in design code | $random or $urandom outside a testbench | None |
| Missing timescale | A testbench with delays and no `timescale | Add `timescale 1ns/1ps |
A line the engine already flags keeps only the engine's diagnostic, so one mistake never shows twice.
Problems
The Problems section of the rail lists every diagnostic in the project, and a failed build's cause when it names a source line. F8 and ⇧F8 walk through them from the cursor. Right click one to copy it or ask the assistant about it.
Resources as you type
After the check, a background synthesis for the project's device family counts each module. The Hierarchy shows the LUTs beside each module, dimmed while they are recomputed.