An EDA Playground alternative.
Run Verilog on your own computer, trace any value to its cause, and take the design to an open FPGA board, in one tab.
// Counts from 0 to MAX while en is high, then wraps to 0. wrap is high on the cycle that wraps.module counter #( parameter int WIDTH = 8, parameter int MAX = 9) ( input logic clk, input logic rst, input logic en, output logic [WIDTH-1:0] count = '0, output logic wrap); always_ff @(posedge clk) begin if (rst) count <= '0; else if (en) count <= (count == MAX - 1) ? '0 : count + 1'b1; end assign wrap = en && (count == MAX);endmoduleWhy is count 0 at 100 ns?
count0expected 9at 95 ns
16count <= (count == MAX - 1) ? '0 : count + 1'b1;
if (rst) was false; if (en) was true; rst 0, en 1, count 8
count1 to 8over 8 edges, 15 ns to 85 ns
16count <= (count == MAX - 1) ? '0 : count + 1'b1;
if (rst) was false; if (en) was true; rst 0, en 1, count 7
rst0at 15 ns
7input logic rst,
rst is a primary input, set by the testbench.
RTL++ and EDA Playground
EDA Playground, from Doulos, runs HDL on its servers with a wide choice of simulators, and is a staple for UVM tutorials. Here is how the two differ.
| Aspect | RTL++ | EDA Playground |
|---|---|---|
| Where simulation runs | In your browser, on your computer | On EDA Playground's servers |
| Simulators | Icarus Verilog, with the netlist simulator checking every run | A choice of open source and commercial simulators |
| UVM and commercial simulators | Not offered | Offered |
| Waveforms | In the workspace, with a trace of the cause of any value | EPWave, its waveform viewer |
| FPGA bitstreams and flashing | iCE40 and ECP5 bitstreams, flashing iCEBreaker and ULX3S over USB | Not offered |
| Starting a project | A blank module with a test, an import from GitHub, or a description the assistant builds | Shared playgrounds |
| Sharing | A link to the project, or to one moment of a failing run | A link to the playground |
What you gain
- Why this value
- Select a value in the waveform and follow the chain of causes back to the line that produced it.
- Two simulators on every run
- A test reads Passed only when Icarus Verilog and a simulator running your synthesized netlist agree.
- A path to hardware
- Synthesis, place and route, bitstream and flashing, without leaving the tab.
- Views of the design
- A schematic and state machines generated from the elaborated design, linked to the code and the waveform.
Questions
What is a good alternative to EDA Playground?
If you work in Verilog or SystemVerilog for FPGAs or a course, RTL++ runs your tests in the browser, explains any value in the waveform and builds for open FPGA boards. If you need UVM or a commercial simulator, EDA Playground remains the better fit.
Is it free?
Yes. Simulation, waveforms, synthesis and FPGA builds run on your computer and are free. Paid plans add stronger assistant models.
Can I bring my EDA Playground code?
Yes. Paste your design and testbench into a project, name the testbench module tb_ and press Run. Testbenches do not need $dumpfile or $dumpvars: every run records its signals.
Does my code leave my computer?
Not to simulate it. It is saved to your account while you are signed in, and reaches the assistant only when you ask it something.