A Verilog simulator that runs in your browser.
Icarus Verilog runs every test, a second simulator checks it against the synthesized netlist, and every value in the waveform can tell you why. Nothing to install.
// Counts from 0 to MAX while en is high, then wraps to 0. wrap is high on the cycle that wraps.module counter #( parameter int WIDTH = 8, parameter int MAX = 9) ( input logic clk, input logic rst, input logic en, output logic [WIDTH-1:0] count = '0, output logic wrap); always_ff @(posedge clk) begin if (rst) count <= '0; else if (en) count <= (count == MAX - 1) ? '0 : count + 1'b1; end assign wrap = en && (count == MAX);endmoduleWhy is count 0 at 100 ns?
count0expected 9at 95 ns
16count <= (count == MAX - 1) ? '0 : count + 1'b1;
if (rst) was false; if (en) was true; rst 0, en 1, count 8
count1 to 8over 8 edges, 15 ns to 85 ns
16count <= (count == MAX - 1) ? '0 : count + 1'b1;
if (rst) was false; if (en) was true; rst 0, en 1, count 7
rst0at 15 ns
7input logic rst,
rst is a primary input, set by the testbench.
What happens when you press Run
- Finds your tests
- Every module named tb_ is a test. A testbench prints PASS and calls $finish when all is well, or stops with $fatal and a sentence.
- Runs Icarus Verilog
- Four-state simulation of Verilog and the SystemVerilog Icarus accepts, compiled and run in the tab.
- Checks it twice
- The netlist simulator replays the synthesized netlist of your design on the same inputs. A test passes only when both agree.
- Records every signal
- The waveform holds every signal of the testbench and the design. You never write $dumpfile or $dumpvars.
- Shows values in the code
- With the waveform cursor on a time, each signal in the editor shows its value at that time.
- Stops runaway runs
- A run stops after 60 s or 268 MB of waveform data, whichever comes first, and says which.
RTL++ and a local simulator
Icarus Verilog on your own machine is a fine simulator. Here is what changes when it runs in the browser with the rest of the workspace.
| Aspect | RTL++ | Icarus on your computer |
|---|---|---|
| Install | None, it runs in the browser | Icarus Verilog, a waveform viewer and a terminal |
| Second simulator | The netlist simulator, on every run | None by default |
| Waveforms | Built in, opened from the test | A separate viewer such as GTKWave, after $dumpvars |
| Why a value is what it is | A chain of causes back to the line | Read the waveform by hand |
| Synthesis and FPGA builds | Yosys and nextpnr in the same tab | Separate tools |
| Sharing | A link to the project, or to one moment of a run | Send the files |
Questions
Is there a free online Verilog simulator?
Yes. RTL++ runs Icarus Verilog in your browser, free, with nothing to install, and checks each run with a second simulator.
Which version of Verilog does it accept?
What Icarus Verilog accepts with its 2012 generation flag: Verilog 2005 and the common synthesizable parts of SystemVerilog, such as logic, always_ff, always_comb, enums and int parameters.
Does my code leave my computer when I simulate?
No. Compiling and simulating happen in the browser tab. Your files reach RTL++'s servers only to be saved to your account while you are signed in, and reach the assistant only when you ask it something.
Can I see waveforms?
Yes. Every run records the signals of the testbench and the design, and the waveform dock shows buses in hex, decimal, binary or by state name.
What happens when the two simulators disagree?
The test reads Simulators disagree, names the first signal and time that differ, and suggests the likely cause, such as a race between processes or unknown values. It is never shown as a pass.