Launch boards

The FPGA boards RTL++ supports: the device, clock, starting template, constraint file and flashing route of each.

Each FPGA board's pin map is checked against the vendor's own constraint file, and every template for it writes its constraint file from that map.

iCEBreaker

Made by: 1BitSquared
Device: iCE40 UP5K in the SG48 package
Clock: 12 MHz
Pin constraints: icebreaker.pcf, written from the board's pin map
On the board lens: 7 LEDs, a two digit 7-segment display and 4 buttons
Flashing: Flash writes the board's configuration flash over WebUSB, erasing, writing and verifying it, then checks that the FPGA started.
Good to know: LEDR, LEDG and BTN are active low. LED1 to LED5 and BTN1 to BTN3 are on the snap-off part and are active high.

Made by: Radiona
Device: ECP5 85F in the CABGA381 package
Clock: 25 MHz
Pin constraints: ulx3s.lpf, written from the board's pin map
On the board lens: 8 LEDs, 7 buttons and 4 switches
Flashing: Flash runs openFPGALoader over WebUSB and loads the FPGA directly, so the design runs until the board loses power.
Good to know: The power button reads 0 when pressed. The other buttons and the switches read 1.

Made by: Radiona
Device: ECP5 12F in the CABGA381 package
Clock: 25 MHz
Pin constraints: ulx3s.lpf, written from the board's pin map
On the board lens: 8 LEDs, 7 buttons and 4 switches
Flashing: Flash runs openFPGALoader over WebUSB and loads the FPGA directly, so the design runs until the board loses power.
Good to know: The power button reads 0 when pressed. The other buttons and the switches read 1.

Made by: Sipeed
Device: Gowin GW1NR-9 in the QN88 package
Clock: 27 MHz
Pin constraints: tangnano9k.cst, written from the board's pin map
On the board lens: 6 LEDs and 2 buttons
Flashing: Not from the browser yet. Builds for Gowin stop after synthesis, so the bitstream comes from the Gowin IDE or apicula.
Good to know: The LEDs are active low, and the buttons read 0 when pressed. Synthesis only: bitstreams for Gowin are not built in the browser yet.

Made by: Greg Davill
Device: ECP5 25F in the CSFBGA285 package
Clock: 48 MHz
Pin constraints: orangecrab.lpf, written from the board's pin map
On the board lens: 1 RGB LED and 1 button
Flashing: Download the bitstream and program it with openFPGALoader. The Build view shows the command.
Good to know: The RGB LED and the user button are active low.

Made by: Tiny Tapeout
Device: ASIC, no FPGA
Clock: 10 MHz
Pin constraints: None. The design uses the fixed Tiny Tapeout ports.
On the board lens: a one digit 7-segment display, 1 button and 8 switches
Flashing: None. The board carries a Tiny Tapeout chip, so a project here runs in simulation and on the board lens.
Good to know: Silicon, not an FPGA. A project is built for the shuttle, so this board runs in simulation only.