Your first project
Open RTL++, create a project, run its test, read the waveform, change the design, and build it. Your first Verilog project in about two minutes.
Create a project
Go to /app. On a first visit, Projects offers three ways to start: Blank project, Describe it, and Import. Choose Blank project and Create: the project opens with top.sv and its test, tb_top.sv. Later, New project at the top of Projects offers the same three.
No account is needed to start. Projects are saved on this device; sign in to keep them in your account and open them anywhere.
Run the tests
- Press Run in the top bar, or
⌘Enter(Ctrl+Enteron Windows and Linux). Every module whose name starts withtb_is a test. - The first run downloads the simulator once and says so in the Tests rail. After that a run starts straight away.
- Each test reads Passed, Failed at a time, or Stopped, in the Tests rail. The waveform dock opens with every signal under the testbench.
Read the result
- Click in the waveform to place the cursor. The value of each signal at that time shows beside its name, and beside each line of your code that names it.
- Hold
⌥and click a value to see why it has it: the line that set it, the values that mattered, and the clock edge, back to its cause. See Why this value. - Press
]and[to move the cursor to the next or previous edge.⌘Jhides and shows the dock.
Change it and build
- Edit the design. Diagnostics follow as you type, and the test rows dim to show they ran before the edit. Run again to refresh them.
- Press Build or
⌘B. The Build view lists the steps as they finish, then the utilization, the maximum clock frequency and the bitstream. - With the board plugged in, press Flash. See Flashing for which boards flash from the browser.