Building
Build an RTL++ project for an iCE40 or ECP5 FPGA in the browser: the steps, utilization against the device, maximum clock frequency, the worst paths and the bitstream.
Press Build in the top bar or ⌘B. The Build lens opens beside the code and lists each step in words as it finishes: Synthesized, Placed, Routed, Bitstream ready. Press Stop to cancel.
A build needs a top module, a device and, for a board, its pin constraint file: .pcf for iCE40 and .lpf for ECP5. Choose the board, device and constraint file at the top of the Build lens or in the Inspector, and the top module in the Inspector.
Utilization
A table of what the design uses against what the device has, after placement: logic cells or LUTs, flip-flops, block RAM, DSP, I/O and PLLs, with the share of each. A resource the design needs more of than the device has reads over 100% in red.
Timing
The maximum frequency of each clock, against the target when one is set. Every figure is labelled Estimate, nextpnr model for the device, not sign-off, with the seed it came from: nextpnr's delay model is fitted to the silicon, not a sign-off timer.
Below it, the worst paths, slowest first: where each starts and ends, its delay, and the lines of your code it passes through, each one a link.
The bitstream
A finished build offers its bitstream for download, named after the top module: .bin for iCE40, .bit for ECP5. Flash programs a connected board. See Flashing.
Show log has the full output of every tool. After an edit, the results stay and say Code changed since this build.
When a build fails
The reason is one sentence, with the source line when there is one, and that line also appears in Problems.