Digital logic, in the browser.
Write Verilog and SystemVerilog, run every test in two simulators, trace any value back to the line that made it, and build for open FPGAs. Nothing to install.
// Counts from 0 to MAX while en is high, then wraps to 0. wrap is high on the cycle that wraps.module counter #( parameter int WIDTH = 8, parameter int MAX = 9) ( input logic clk, input logic rst, input logic en, output logic [WIDTH-1:0] count = '0, output logic wrap); always_ff @(posedge clk) begin if (rst) count <= '0; else if (en) count <= (count == MAX - 1) ? '0 : count + 1'b1; end assign wrap = en && (count == MAX);endmoduleWhy is count 0 at 100 ns?
count0expected 9at 95 ns
16count <= (count == MAX - 1) ? '0 : count + 1'b1;
if (rst) was false; if (en) was true; rst 0, en 1, count 8
count1 to 8over 8 edges, 15 ns to 85 ns
16count <= (count == MAX - 1) ? '0 : count + 1'b1;
if (rst) was false; if (en) was true; rst 0, en 1, count 7
rst0at 15 ns
7input logic rst,
rst is a primary input, set by the testbench.
Recorded from a real run: the Counter design with line 16 changed to (count == MAX - 1) ? '0 : count + 1'b1.
Every value has a reason.
Select a value in the waveform and ask why. RTL++ walks back through the logic and the clock edges to the line and the inputs that produced it, and marks the first step where the value parts from the one the test expected.
From the failure
tb_counter stopped at 100 ns with “After 9 cycles count is 0, expected 9”. The expected 9 came from that sentence.
To the line
The first step lands on line 16 of counter.sv, where count became 0 at the edge at 95 ns.
Through the clock edges
Eight edges of ordinary counting fold into one row, so the chain stays three steps long.
A pass means two simulators agreed.
Every test runs in Icarus Verilog and, alongside it, in a simulator that runs the netlist Yosys built from your design. A result is shown only when both say the same.
tb_counter, as shipped
Passed
The netlist replay agreed on 57 of 57 samples.
tb_counter, line 16 changed
Failed at 100 ns
After 9 cycles count is 0, expected 9. The netlist replay agreed on 21 of 21 samples.
- Icarus Verilog
- Runs every testbench module named tb_, four-state, with the testbench's own messages as the result.
- A second simulator
- Replays the synthesized netlist of your design on the same inputs and compares every output before each clock edge.
- Simulators disagree
- When the two differ, the test says so with the first differing signal and time, and never reads Passed.
- Unknown values
- Any X that reaches an output or a branch condition is listed with the time it first appears.
From test to board.
Synthesis, place and route and a bitstream for 11 iCE40 and ECP5 devices, in the tab. Flash iCEBreaker and ULX3S over USB from Chrome or Edge.
| Board | FPGA | Clock | In the browser | Flash over USB |
|---|---|---|---|---|
| iCEBreaker | iCE40 UP5K | 12 MHz | Bitstream in the browser | Yes |
| ULX3S 85F | ECP5 85F | 25 MHz | Bitstream in the browser | Yes |
| ULX3S 12F | ECP5 12F | 25 MHz | Bitstream in the browser | Yes |
| Tang Nano 9K | Gowin GW1NR-9 | 27 MHz | Synthesis and constraint checks | No |
| OrangeCrab | ECP5 25F | 48 MHz | Bitstream in the browser | No |
| Tiny Tapeout demo board | ASIC, no FPGA | 10 MHz | Simulation | No |
An assistant that shows its evidence.
It works through 18 tools, from reading files to tracing a value, and every test run or build it makes is evidence it has to cite.
- Reads your project
- Files, symbols and diagnostics, with line numbers, through the same tools you use.
- Runs the engines
- Tests, synthesis and builds go through the workspace, so its runs show up in your Tests rail and waveform.
- Cites its evidence
- It may say tests pass or a design meets timing only by citing a run from that answer. Anything else is marked Not verified.
Share the moment, not a screenshot.
A moment link reopens the project at the same test, time, file and line. Send it to a teammate or a TA and they land on the failure.
rtlpp.vercel.app/app?p=project#m=test:tb_counter;t:100000000;f:counter.sv;l:16;lens:code
- View or edit
- A share link adds the person to the project at the role you chose when they sign in.
- Viewers run tests
- A read-only viewer can still run the tests on their own machine without changing anything.
- Every view
- Code, Schematic, State machine, Board and Build, all from the same elaborated design.
Questions
What is RTL++?
A digital logic workspace in the browser: write Verilog and SystemVerilog, run every testbench in two simulators, read the waveform, trace any value back to the line that produced it, and build bitstreams for open FPGAs. Nothing to install.
Which simulators does it use?
Icarus Verilog, compiled to WebAssembly, runs every testbench. Alongside it, a second simulator replays the netlist Yosys synthesized from your design on the same inputs. A test reads Passed only when both agree.
Does my code leave my computer?
Simulation, synthesis and builds run in your browser tab. Projects are saved on your device, and in your account when you sign in. Only the assistant sends text to a model, and only when you ask it something.
Which FPGAs can I build for?
11 iCE40 and ECP5 devices, with place and route and a bitstream in the tab. Boards with a full build: iCEBreaker, ULX3S and OrangeCrab. Flash iCEBreaker and ULX3S over USB from Chrome or Edge.
Are there limits on a run?
A test run stops after 60 s or 268 MB of waveform data, whichever comes first, and says which limit it reached.
How do I start?
Open one of 14 templates, each with its tests, or one of 25 practice problems, and press Run. You can also import a zip, a folder, a GitHub repository or a Vivado project.
Can I work with other people?
Yes. Share a project at a role, viewer, commenter or editor, by email or by link. Collaborators see who else is in the project, edit together with changes merged file by file, and leave comments on a line or on a moment in the waveform.
How does it relate to Spice++?
RTL++ is the digital twin of Spice++, the analog circuit simulator. One account and one subscription cover both, with one assistant allowance.