SystemVerilog, online.
Write synthesizable SystemVerilog and self-checking testbenches, simulate them in Icarus Verilog and synthesize them with Yosys, all in one browser tab.
module uart_rx #( parameter int CLKS_PER_BIT = 104 // 12 MHz / 115200 baud) ( input logic clk, input logic rx, output logic [7:0] data, output logic valid); typedef enum logic [1:0] { IDLE, START, DATA, STOP } state_t; state_t state = IDLE; logic [$clog2(CLKS_PER_BIT)-1:0] ticks = '0; logic [2:0] bit_index = '0; logic [7:0] shift = '0; logic [7:0] data_q = '0; logic valid_q = 1'b0; // Two flip-flops bring the asynchronous line into the clock domain. logic rx_meta = 1'b1; logic rx_sync = 1'b1; always_ff @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end- IDLEstays, or goes to START
- STARTstays, or goes to DATA or IDLE
- DATAstays, or goes to STOP
- STOPstays, or goes to IDLE
The UART receiver design, and the state machine RTL++ extracted from the netlist of its tb_uart_rx run.
What it understands
The synthesizable SystemVerilog that Icarus Verilog and Yosys both accept, which covers what an FPGA design and its testbench usually need.
- logic and int
- Four-state logic for signals, int for parameters, with '0 and '1 fills.
- always_ff and always_comb
- Clocked and combinational blocks, as Icarus and Yosys both read them.
- Enums
- typedef enum state types. State names show in the waveform, in values in the code and in the State machine view.
- Self-checking testbenches
- $display, $fatal with a message and $finish, run by Icarus Verilog. A test passes when it prints PASS and finishes.
- Functions and widths
- function automatic, and $clog2 to size a counter from a parameter.
- Synthesis
- Yosys reads the same files for the schematic, the state machines and FPGA builds.
Questions
Can I compile SystemVerilog online for free?
Yes. RTL++ compiles and simulates SystemVerilog in your browser with Icarus Verilog, and synthesizes it with Yosys, with nothing to install.
Does it support UVM?
No. UVM needs classes, randomization and a commercial simulator. RTL++ runs synthesizable SystemVerilog with self-checking testbenches, the style most digital design courses and FPGA projects use.
Which SystemVerilog features work?
The synthesizable core that Icarus Verilog's 2012 mode and Yosys both accept: logic, always_ff, always_comb, enums, int parameters and automatic functions, plus the system tasks a testbench needs.
Can I see my state machine?
Yes. The State machine view extracts state machines from the elaborated design, with state names from your enum, and shows the state at the waveform cursor. The uart_rx machine above was extracted that way.