An FPGA simulator, from test to bitstream.
Test your design, watch it drive the board, build the bitstream and flash it, in one browser tab with nothing installed.
Simulate with the board around it
The Board view draws the board's LEDs, buttons, switches and displays, driven by your design in the digital simulator. Click a button and the design sees it.
Build in the tab
Yosys synthesizes, nextpnr places and routes, and the bitstream is packed, for 11 iCE40 and ECP5 devices. Utilization reads against the device's capacity as nextpnr counts it.
Flash over USB
openFPGALoader runs in the browser and programs iCEBreaker and ULX3S over WebUSB in Chrome or Edge. When the browser cannot reach the board, you get one sentence with the cause and the fix, and the bitstream to download.
A real build, as it reads.
The Blink design for the iCEBreaker, built in the browser engines. The bitstream hash is the same on every run with seed 1.
| Logic cells | 36 | of 5,280 |
|---|---|---|
| Flip-flops | 24 | of 5,280 |
| Carry | 21 | of 5,280 |
| Global buffers | 2 | of 8 |
| Block RAM | 0 | of 30 |
| DSP | 0 | of 8 |
| I/O | 3 | of 39 |
| PLL | 0 | of 1 |
clk reaches 58.98 MHz against a 12 MHz target. Estimate, nextpnr model for iCE40 UP5K (sg48), not sign-off.
Boards
Pin maps checked against each vendor's constraint file, and a starting project with tests for each.
| Board | FPGA | Clock | In the browser | Flash over USB |
|---|---|---|---|---|
| iCEBreaker | iCE40 UP5K | 12 MHz | Bitstream in the browser | Yes |
| ULX3S 85F | ECP5 85F | 25 MHz | Bitstream in the browser | Yes |
| ULX3S 12F | ECP5 12F | 25 MHz | Bitstream in the browser | Yes |
| Tang Nano 9K | Gowin GW1NR-9 | 27 MHz | Synthesis and constraint checks | No |
| OrangeCrab | ECP5 25F | 48 MHz | Bitstream in the browser | No |
| Tiny Tapeout demo board | ASIC, no FPGA | 10 MHz | Simulation | No |
Questions
Can I simulate an FPGA design without the board?
Yes. Tests run in Icarus Verilog with a second simulator checking them, and the Board view runs the design live against a drawing of the board, so you can press its buttons and watch its LEDs.
Can I build a bitstream in the browser?
For iCE40 and ECP5 FPGAs, yes. Yosys, nextpnr and the bitstream packer run as WebAssembly. Each build records its seed and tool versions, and the same seed and sources give the same bitstream.
Is the timing report sign-off?
No. Maximum frequency comes from nextpnr's timing model for the device and is labelled as an estimate on every result. It is a good guide for open FPGA boards, not a sign-off analysis.
Which browsers can flash a board?
Chrome and Edge, which support WebUSB. Other browsers can build and download the bitstream to load with a local tool.
Blink an LED on your board.
Open RTL++, write the module, choose your board and press Build.