Introduction
RTL++ is a workspace for Verilog and SystemVerilog in the browser: write a design, run its tests in two simulators, trace any value to its cause, build for an open FPGA and flash the board.
Every engine runs in your browser: Icarus Verilog for simulation, Yosys with slang for diagnostics and synthesis, nextpnr for place and route, and openFPGALoader for programming. Nothing is installed and nothing waits in a queue.
What it does
- A blank project starts with a module and a passing testbench. See Projects and saving.
- Live diagnostics as you type, with quick fixes for latches, sensitivity lists and blocking assignments. See Diagnostics.
- Tests that pass only when Icarus and a second simulator agree on every sample. See Two simulators.
- Waveforms with cursors, measurement, and values written beside your code. See Reading waveforms.
- Why this value: the chain of lines and clock edges that produced any value. See Why this value.
- Builds for iCE40 and ECP5 with utilization and timing, and flashing over USB. See Building and Flashing.
- An assistant that reads, edits, runs and traces through the same engines, and cites a run for every claim. See Working with the assistant.
What downloads, and when
Each engine downloads the first time it is needed, with one line saying so, then stays in the browser for later sessions. Every file is checked against a pinned SHA-256 before it runs.
| Engine | Downloaded on | Size |
|---|---|---|
| Icarus Verilog | The first test run | 3 MB |
| Yosys, with slang for SystemVerilog | The first diagnostics | 78 MB |
| nextpnr for iCE40 | The first iCE40 build | 235 MB |
| nextpnr for ECP5 | The first ECP5 build | 176 MB |
| openFPGALoader | The first flash of an ECP5 board | 8 MB |
How these docs are organized
- Start here
- Your first project, the workspace and the keyboard shortcuts.
- Projects and files
- Starting a project, saving, the rtlpp.toml manifest, files, import and export.
- Editor
- Diagnostics, navigation, find and replace, and values in code.
- Simulation and tests
- Testbenches, the Tests rail, and how two simulators decide a pass.
- Waveforms
- Reading lanes and buses, cursors, measuring and moving through time.
- Why this value
- Tracing a value back to the line that caused it.
- Schematic and state machines
- The views drawn from the elaborated design.
- Build
- Synthesis, place and route, devices, seeds and timing.
- Boards and flashing
- Each board, the board lens, and programming hardware.
- The assistant
- What it can do, how it proves claims, models and allowance.
- Sharing and moments
- Links to a project and to a moment in it.
- Account and billing
- One account, plan and allowance shared with Spice++.