ULX3S, from Verilog to a flashed board.
The Radiona ULX3S carries an ECP5 85F or an ECP5 12F, with 8 LEDs, 7 buttons, 4 switches, a USB serial port and a digital video port. RTL++ simulates your design on it, builds the bitstream in the tab and flashes it over USB.
| Board | Device | Clock | Logic cells | Block RAM | In the browser | Flash over USB |
|---|---|---|---|---|---|---|
| ULX3S 85F | ECP5 85F | 25 MHz | 83,640 | 208 | Bitstream in the browser | Yes |
| ULX3S 12F | ECP5 12F | 25 MHz | 24,288 | 56 | Bitstream in the browser | Yes |
The power button reads 0 when pressed. The other buttons and the switches read 1.
Pin map
Every pin is checked against the vendor's constraint file, so a constraint .lpf file written from it matches the board.
| Signal | Pin | Kind | Direction | Active |
|---|---|---|---|---|
| clk_25mhz | G2 | Clock, 25 MHz | Input | High |
| ftdi_rxd | L4 | Serial | Output | High |
| ftdi_txd | M1 | Serial | Input | High |
| led0 | B2 | LED | Output | High |
| led1 | C2 | LED | Output | High |
| led2 | C1 | LED | Output | High |
| led3 | D2 | LED | Output | High |
| led4 | D1 | LED | Output | High |
| led5 | E2 | LED | Output | High |
| led6 | E1 | LED | Output | High |
| led7 | H3 | LED | Output | High |
| btn0 | D6 | Button | Input | Low |
| btn1 | R1 | Button | Input | High |
| btn2 | T1 | Button | Input | High |
| btn3 | R18 | Button | Input | High |
| btn4 | V1 | Button | Input | High |
| btn5 | U1 | Button | Input | High |
| btn6 | H16 | Button | Input | High |
| sw0 | E8 | Switch | Input | High |
| sw1 | D8 | Switch | Input | High |
| sw2 | D7 | Switch | Input | High |
| sw3 | E7 | Switch | Input | High |
Also mapped: 56 GPIO pins and 8 Video pins.
Questions
Can I program the ULX3S 85F from the browser?
Yes, in Chrome or Edge, which support WebUSB. RTL++ runs openFPGALoader in the tab and writes the FPGA's configuration memory, so the design runs until power is removed. Other browsers can download the bitstream.
Can I program the ULX3S 12F from the browser?
Yes, in Chrome or Edge, which support WebUSB. RTL++ runs openFPGALoader in the tab and writes the FPGA's configuration memory, so the design runs until power is removed. Other browsers can download the bitstream.
Which FPGA is on the ULX3S?
An ECP5 85F on the ULX3S 85F or an ECP5 12F on the ULX3S 12F, each with a 25 MHz clock and the same pin map.
Do I need to install a toolchain?
No. Yosys, nextpnr, Icarus Verilog and openFPGALoader run in the browser as WebAssembly, so there is no oss-cad-suite, apio or vendor tool to install.