Import and export

Bring an existing Verilog or SystemVerilog project into RTL++ as a zip, and export any project as a plain zip that builds with the open tools outside RTL++.

Export

Export as zip in the command bar, in More at phone width, or in a project's menu on Projects, downloads every file of the project unchanged, plus rtlpp.toml. Nothing in it needs RTL++: the sources and the constraint file build with Yosys and nextpnr on your own machine.

Import

Import, under New project or the More menu on Projects, brings in a zip, a folder, loose files or a public GitHub repository; dropping any of them on the home, or pasting a github.com link into ⌘K, does the same. A Vivado project (.xpr) inside any of them is read too: its sources, constraints and top module. Before anything opens, the review page lists the sources, testbenches, constraints and other files, the likely top module and a guess at the target, each with its reason; change any of them, then Create. Source files keep their exact bytes, so a project survives an import and export round trip unchanged.

HDL, headers, constraint files (.pcf, .lpf, .cst, .xdc, .sdc), and text such as Markdown, TOML, YAML, Python, assembly and memory images (.hex, .mem) are read. Other files, such as build output, are skipped, and so are hidden folders.
An rtlpp.toml in the zip sets the name, top module, board, device and build settings. Without one, the top module is the first design module that no other module instantiates.
A zip may be up to 10 MB, hold up to 500 files, and unpack to up to 40 MB.