Tang Nano 9K, simulated and synthesized.
The Sipeed Tang Nano 9K carries a Gowin GW1NR-9, with 6 LEDs, 2 buttons, a USB serial port and a digital video port. RTL++ simulates your design and synthesizes it against the board's pins.
| Board | Device | Clock | Logic cells | Block RAM | In the browser | Flash over USB |
|---|---|---|---|---|---|---|
| Tang Nano 9K | Gowin GW1NR-9 | 27 MHz | 8,640 | 26 | Synthesis and constraint checks | No |
The LEDs are active low, and the buttons read 0 when pressed. Synthesis only: bitstreams for Gowin are not built in the browser yet.
Pin map
Every pin is checked against the vendor's constraint files, so a constraint .cst file written from it matches the board.
| Signal | Pin | Kind | Direction | Active |
|---|---|---|---|---|
| clk | 52 | Clock, 27 MHz | Input | High |
| led0 | 10 | LED | Output | Low |
| led1 | 11 | LED | Output | Low |
| led2 | 13 | LED | Output | Low |
| led3 | 14 | LED | Output | Low |
| led4 | 15 | LED | Output | Low |
| led5 | 16 | LED | Output | Low |
| btn_reset | 4 | Button | Input | Low |
| btn_user | 3 | Button | Input | Low |
| uart_tx | 17 | Serial | Output | High |
| uart_rx | 18 | Serial | Input | High |
Also mapped: 4 Video pins.
Questions
Can I build a bitstream for the Tang Nano 9K?
Not in the browser yet: place and route for its Gowin GW1NR-9 is not among the engines that run in the tab. Simulation, the board view, and synthesis against the board's constraint file all work, and the project exports as plain files for the vendor's tools.
Which FPGA is on the Tang Nano 9K?
The Tang Nano 9K carries a Gowin GW1NR-9, with a 27 MHz clock.
Do I need to install a toolchain?
Not to simulate and synthesize: Icarus Verilog and Yosys run in the browser as WebAssembly. A bitstream for this board still needs a toolchain on your computer.