Boards
Tiny Tapeout, simulated in the browser.
The Tiny Tapeout demo board, with 8 switches and a 1 digit 7-segment display. RTL++ simulates the design with the board's parts around it.
| Board | Device | Clock | Logic cells | Block RAM | In the browser | Flash over USB |
|---|---|---|---|---|---|---|
| Tiny Tapeout demo board | ASIC, no FPGA | 10 MHz | None | None | Simulation | No |
Silicon, not an FPGA. A project is built for the shuttle, so this board runs in simulation only.
Pin map
Every pin is checked against the vendor's constraint file, so a constraint interface written from it matches the board.
| Signal | Pin | Kind | Direction | Active |
|---|---|---|---|---|
| clk | Clock, 10 MHz | Input | High | |
| rst_n | Reset | Input | Low | |
| ena | Reset | Input | High | |
| ui0 | Switch | Input | High | |
| ui1 | Switch | Input | High | |
| ui2 | Switch | Input | High | |
| ui3 | Switch | Input | High | |
| ui4 | Switch | Input | High | |
| ui5 | Switch | Input | High | |
| ui6 | Switch | Input | High | |
| ui7 | Switch | Input | High |
Also mapped: 8 PMOD pins.
Questions
Do I need to install a toolchain?
No. Icarus Verilog and Yosys run in the browser as WebAssembly, so the design simulates with nothing installed.