Boards
OrangeCrab, from Verilog to a flashed board.
The Greg Davill OrangeCrab carries an ECP5 25F, with 3 LEDs and 1 button. RTL++ simulates your design on it, builds the bitstream in the tab.
| Board | Device | Clock | Logic cells | Block RAM | In the browser | Flash over USB |
|---|---|---|---|---|---|---|
| OrangeCrab | ECP5 25F | 48 MHz | 24,288 | 56 | Bitstream in the browser | No |
The RGB LED and the user button are active low.
Pin map
Every pin is checked against the vendor's constraint files, so a constraint .lpf file written from it matches the board.
| Signal | Pin | Kind | Direction | Active |
|---|---|---|---|---|
| clk48 | A9 | Clock, 48 MHz | Input | High |
| rgb_r | K4 | LED | Output | Low |
| rgb_g | M3 | LED | Output | Low |
| rgb_b | J3 | LED | Output | Low |
| usr_btn | J17 | Button | Input | Low |
| rst_n | V17 | Reset | Input | Low |
Also mapped: 19 GPIO pins.
Questions
Can I build a bitstream for the OrangeCrab?
Yes. Synthesis, place and route and the bitstream all run in the browser. Flashing this board from the browser is not offered yet, so download the bitstream and load it with the board's own tool.
Which FPGA is on the OrangeCrab?
The OrangeCrab carries an ECP5 25F, with a 48 MHz clock.
Do I need to install a toolchain?
No. Yosys, nextpnr, Icarus Verilog run in the browser as WebAssembly, so there is no oss-cad-suite, apio or vendor tool to install.